1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to an integrated circuit which employs a multilevel interconnect structure having a layer of air which separates conductors within each level of interconnect and conductors between levels of interconnect. Pillars are spaced within the layer of air to support conductors within each interconnect level. The conductors are made rigid using a layer of anodized aluminum formed on each conductor. Conductors on dissimilar levels are electrically connected by contacts arranged within select pillars.
2. Description of the Relevant Art
Fabrication of an integrated circuit involves placing numerous devices on a single monolithic substrate. Each device is electrically isolated from the others, but later in the fabrication sequence specific devices are electrically interconnected so as to implement desired circuit function. Interconnect of those devices often takes place on more than one elevational level, each level having a set of substantially coplanar interconnect conductors. Numerous levels of interconnect arranged above a monolithic substrate is generally referred to as a multilevel interconnect structure.
A level of interconnect is made simultaneously using lithography techniques from electrically conductive material, a suitable material includes Al, Ti, Ta, W, Mo, Cu, polysilicon, or a combination thereof. The multilevel interconnect structure is deposited layer-by-layer upon a semiconductor substrate, a suitable substrate includes any type of material which can retain dopant ions and the isolated conductivity regions brought about by those ions. Typically, a substrate is a silicon-based material which receives P-type or N-type ions.
Generally speaking, each conductor within a level of conductors is dielectrically spaced from one another by a relatively small distance. That spacing to some extent determines interlevel capacitance between conductors on dissimilar levels and intralevel capacitance between conductors on the same level. Thus, a multilevel interconnect structure comprises conductors which are horizontally and vertically spaced from each other across a semiconductor topography. Dielectric constant of dielectric material arranged horizontally and vertically between conductors also determines intralevel and interlevel capacitance, and interlevel and intralevel capacitance determine, to some extent, the electrical performance of a signal forwarded through a conductor. For example, large intralevel and interlevel capacitance not only causes noise cross-coupling between conductors, but also increases the propagation delay of a signal forwarded through the conductors.
Modern integrated circuits generally employ close conductor spacing which cause unacceptably large propagation delays and cross-talk noise within the conductors. Even if a conductor does not transition, it nonetheless receives cross-talk noise from neighboring, closely spaced conductors which do. It is thereby important to minimize propagation delay and cross-talk noise problems by paying close attention to the dielectric properties of dielectrics which are horizontally or vertically spaced between conductors. The primary dielectric property of concern is the dielectric constant. By lowering the dielectric constant, problems of propagation delay and cross-coupling can be reduced even when conductor spacings are fairly small.
It would therefore be desirable to employ a dielectric which reduces the intralevel and interlevel capacitance, and thereby reduces propagation delay and cross-coupling noise. A dielectric of lowest possible dielectric constant affords closer spacing between conductors on separate levels or within the same level.